The present invention relates in general to semiconductor devices, particularly to the layout of a semiconductor integrated circuit for realizing reliable operational characteristics.
In the semiconductor integrated circuits, it is generally required that the integrated circuit has input and output circuits that have predetermined, standardized input and output characteristics. For example, the integrated circuits that are used for telecommunications according to the CCITT protocols such as the CCITT v.28, etc., are required to have a standardized impedance or resistance in the input and output signal paths. Generally, there are a number of input or output channels in such integrated circuits, and associated therewith, there are a number of input or output buffer circuits provided in the integrated circuit. With the decreasing size of the integrated circuit chip, these input/output buffer circuits have to be disposed along the periphery of the circuit chip to surround the chip. Each of these input or output buffer circuits includes one or more resistors of which value is determined according to the telecommunication protocol or other industrial standard. Particularly, there are occasions wherein the standard protocol has to be observed exactly. In other words, there are cases wherein the resistors in the input and output buffer circuits are required to have an exact resistance value.
FIG. 1 shows an example of the input buffer circuit, while FIG. 2 shows an example of the output buffer circuit.
Referring to FIG. 1, there is provided an input connection pad 4 of an LSI chip on which a lead wire carrying an input signal is bonded, and the input signal is supplied to an inverter part including a P-channel MOS transistor 5 and an N-channel MOS transistor 6 via a resistor part R including resistors R1 and R2 and a clamping part including diodes D1 and D2. The clamping part clamps the signal to the transistors 5 and 6 and protects the same against surge or other excessive rising of input signal voltage. The signal is subsequently sent to a processing circuit provided inside the LSI chip. The resistor part R provides the required input impedance, and for this purpose, the resistors R1 and R2 are required to have values matching the designed value.
FIG. 2 shows an example of the output circuit.
Referring to FIG. 2, there is provided an inverter circuit including a P-channel MOS transistor 5' and an N-channel MOS transistor 6', and an output signal of a processing circuit inside the LSI chip is supplied to the inverter circuit. In the inverter circuit, a voltage divider including a resistor R3 and a resistor R4 is interposed between the source of the MOS transistor 5' and the drain of the MOS transistor 6'. The voltage divider has a center node that is connected to a connection pad 4'. In this circuit, too, it is desired that the resisters R3 and R4 have respective values exactly adjusted to the designed values.
FIG. 3 shows the layout of the input/output part of a conventional LSI chip in the plan view, wherein the drawing shows only the lower right corner of a chip 1 that includes the output buffer circuit of FIG. 2. In the description hereinafter, the edge of the chip shown at the bottom in the drawing will be referred to as the bottom edge for the sake of convenience, although this edge would not be at the bottom when the chip is set horizontal for the actual use. Similarly, the direction extending vertically in the drawing will be referred to as the vertical direction of the chip for the sake of convenience, although this direction should be horizontal in the actual setting of the chip.
Referring to FIG. 3, the chip 1 has a bottom edge along which the transistor 5' and the transistor 6' are aligned in the vertical direction with the connection pad 4 intervening therebetween. The resistor R3 is provided between the transistor 5' and the connection pad 4, while the resistor R4 is provided between the transistor 6' and the connection pad 4. Further, along the right edge of the chip 1, there is provided the transistors 5' and 6' with the intervening connection pad 4' such that the transistor 5', the connection pad 4' and the transistor 6' are aligned in the horizontal direction.
In order to achieve the desired resistance, the resistors R3 and R4 are generally configured to have a zigzag pattern including a number of elongated resistance strips connected in series. In designing the layout of such resistors, it has been practiced that the elongated resistance strips forming the resistors at the bottom edge of the chip extend in the vertical direction while the resistors provided along the right edge have the elongated resistance strips extending in the horizontal direction.
As already noted, there occurs frequently the case wherein each input or output buffer circuit provided on the chip should have an identical input/output characteristics, including the input or output resistance, wherever it may be located on the chip. Thus, there arises a case in which the output buffer circuit of FIG. 3 at the bottom edge of the chip 1 should have a resistance value for the resistors R3 and R4 that is identical with the resistance value of the resistors R3 and R4 of the output buffer circuit provided at the right edge of the chip 1.
The formation of such a resistance pattern is of course possible, provided that the patterning for forming the resistance strips is controlled exactly. In the actual fabrication process of LSIs, however, there often arises a case in which the pattern is distorted and the desired size of the pattern is different in the two perpendicular directions on the surface of the chip. For example, there arises a case wherein a pattern, that is formed to have a predetermined size, actually has various sizes in various elongating directions.
FIGS. 4(A)-4(D) show an example of such deformation of the pattern.
Referring to the drawings, FIG. 4(A) shows a resistor pattern RX with the predetermined, designed size in the X- and Y-directions. In the illustrated example, the pattern RX has a longitudinal size in the X-direction of 50 .mu.m and a lateral size in the Y-direction of 20 .mu.m. FIG. 4(B) shows the same pattern RX formed on the actual wafer by the photolithographic patterning process. In the formed pattern, designated as RX1 in the drawing, the longitudinal edge in the X-direction is increased by about 10%, while there is an increase in the lateral size of about 5% in the Y-direction. Thus, the pattern RX1 has the longitudinal size of 55 .mu.m in the X-direction and the lateral size of 21 .mu.m in the Y-direction. Although the reason of such a distortion of the pattern is not completely understood, it is believed that these distortions occur from various causes such as the non-flat, curved wafer surface, distortion of the photolithographic mask, error as the time of fabrication of the mask, and the like. When such a distortion occurs, the resistance pattern RX1 of FIG. 4(B) takes a resistance value of r.times.55 .mu.m/21 .mu.m.apprxeq.2.62.times.r ohms, where r represents the surface resistance per unit area.
FIGS. 4(C) and 4(D) show the example of distortion of a vertically elongated pattern RY, wherein the pattern RY represents the as-designed pattern while the pattern RY1 represents the actually formed pattern.
Referring to FIGS. 4(C) and 4(D), the lateral edge extending in the X-direction increases from 20 .mu.m to 22 .mu.m and the longitudinal edge extending in the Y-direction increases from 50 .mu.m to 52.5 .mu.m due to the distortion that increases the size of the pattern in the X-direction by 10% and in the Y-direction by 5%. In this case, the actual pattern RY1 shows a resistance value of r.times.52.5 .mu.m/22 .mu.m.apprxeq.2.37.times.r ohms.
The foregoing examples clearly show that the resistance value may be changed in the actual pattern, depending on the elongating direction of the patterned resistance strip.
When the foregoing problem of distortion of the pattern occurs in the layout pattern of FIG. 3, it will be easily understood that the value of the resistance may differ in the resistance R3 or R4, depending on whether they are provided along the right edge of the chip or along the bottom edge of the chip. When such a difference in the resistance value exists, on the other hand, the output buffer circuit of FIG. 2 would have different output resistances depending on the location on the chip where the circuit is provided. A similar problem arises also in the input buffer circuit of FIG. 1.